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INTEGRATED CIRCUITS
DATA SHEET
TDA9143 I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
Preliminary specification File under Integrated Circuits, IC02 1996 Jan 17
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
FEATURES * Multi-standard colour decoder and sync processor for PAL, NTSC and SECAM * PALplus helper blanking and EDTV-2 blanking * I2C-bus controlled * I2C-bus addresses hardware selectable * Pin compatible with TDA9141 * Alignment free * Few external components * Designed for use with baseband delay lines * Integrated video filters * Adjustable luminance delay * Noise detector with I2C-bus read-out * Norm/no_norm detector with I2C-bus read-out * CVBS or Y/C input, with automatic detection possibility * CVBS output, provided I2C-bus address 8A is used * Vertical divider system * Two-level sandcastle signal * VA synchronization pulse (3-state) * HA synchronization pulse or clamping pulse CLP input/output * Line-locked clock output (6.75 MHz or 6.875 MHz) or stand-alone I2C-bus output port * Stand-alone I2C-bus input/output port * Colour matrix and fast YUV switch * Comb filter enable input/output with subcarrier frequency * Internal bypass mode of external delay line for NTSC applications * Low power standby mode with 3-state YUV outputs * Fast blanking detector with I2C-bus read-out * Blanked or unblanked sync on Yout by I2C-bus bit BSY * Internal MACROVISION gating for the horizontal PLL enabled by bus bit EMG. ORDERING INFORMATION TYPE NUMBER TDA9143 PACKAGE NAME SDIP32 DESCRIPTION plastic shrink dual in-line package; 32 leads (400 mil) GENERAL DESCRIPTION
TDA9143
The TDA9143 is an I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with blanking facilities for PALplus and EDTV-2 signals. The TDA9143 has been designed for use with baseband chrominance delay lines, and has a combined subcarrier frequency/comb filter enable signal for communication with a PAL/NTSC comb filter. The IC can process both CVBS input signals and Y/C input signals. The input signal is available on an output pin, in the event of a Y/C signal, it is added into a CVBS signal. The sync processor provides a two-level sandcastle, a horizontal pulse (CLP or HA pulse, bus selectable) and a vertical (VA) pulse. When the HA pulse is selected, a line-locked clock (LLC) signal is available at the output port pin (6.75 MHz or 6.875 MHz). A fast switch can select either the internal Y signal with the UV input signals, or YUV signals made of the RGB input signals. The RGB input signals can be clamped with either the internal or an external clamping signal. Two pins with an input/output port and an output port of the I2C-bus are available. The I2C-bus address of the TDA9143 is hardware programmable.
VERSION SOT232-1
1996 Jan 17
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
QUICK REFERENCE DATA SYMBOL VCC ICC VCVBS(p-p) VY(p-p) VC(p-p) VY(out) VU(out)(p-p) VV(out)(p-p) VSC(bl) VSC(clamp) VVA VHA VLLC(p-p) VR,G,B(p-p) Vclamp(I/O) Vsub(p-p) VOPORT PARAMETER positive supply voltage supply current CVBS input voltage (peak-to-peak value) luminance input voltage (peak-to-peak value) chrominance burst input voltage (peak-to-peak value) luminance black-white output voltage U output voltage (peak-to-peak value) V output voltage (peak-to-peak value) sandcastle blanking voltage level sandcastle clamping voltage level VA output voltage HA output voltage LLC output voltage amplitude (peak-to-peak value) RGB input voltage (peak-to-peak value) clamping pulse input/output voltage subcarrier output voltage amplitude (peak-to-peak value) port output voltage 0 to 100% saturation standard colour bar standard colour bar top sync-white top sync-white CONDITIONS MIN. 7.2 50 - - - - - - 2.2 4.2 4.0 4.0 250 - - 150 4.0 TYP. 8.0 60 1.0 1.0 0.3 1.0 1.33 1.05 2.5 4.5 5.0 5.0 500 0.7 5.0 200 5.0
TDA9143
MAX. 8.8 70 1.43 1.43 0.6 - - - 2.8 4.8 5.5 5.5 - 1.0 - 300 5.5
UNIT V mA V V V V V V V V V V mV V V mV V
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SDA 6 SCL 5 VCC 7 HPLL 24 SC 10 VA 22 ADDR (CVBS) 15 LCA 16 O PORT/LLC SYNC SEPARATOR HORIZONTAL PLL I2C-BUS VERTICAL SYNC SEPARATOR HA TIMING GENERATOR CLP I/O PORT 26 Y/CVBS
BLOCK DIAGRAM
Philips Semiconductors
TRAP
handbook, full pagewidth
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
VA CLP/HA 11 17
R
G
B
F Uout Vout Yout 18 14 13 12
21 20 19
3 MATRIX ECL ECL TB DELAY YD3-YD0 BPS SWITCH 4
Uin Vin
DELAY 2 2 32 1 SECref -(R-Y) -(B-Y)
4
C DEC
Y CLAMP
SECAM CLOCHE
FILTER TUNING
SECAM DEMOD
SWITCH
2
25
CHROMA SWITCH INA-INB
ACC
CHROMA BANDPASS
CHROMA PLL
HUE
PAL/NTSC DEMOD
8
BIAS
TDA9143
28 FILTref 27 AGND 29 CPLL 30 XTAL 31
ECMB
FSC BUFFER 23
IDENT SYSTEM
9 DGND
XTAL2
MGE039
Preliminary specification
Fscomb
TDA9143
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
PINNING SYMBOL -(R-Y) -(B-Y) Uin Vin SCL SDA VCC DEC DGND SC VA Yout Vout Uout I/O PORT O PORT/LLC CLP/HA PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DESCRIPTION output signal for -(R-Y) output signal for -(B-Y) chrominance U input chrominance V input serial clock input serial data input/output positive supply voltage digital supply decoupling digital ground sandcastle output vertical acquisition synchronization pulse luminance output chrominance V output chrominance U output input/output port output port/line-locked clock output clamping pulse/HA synchronization pulse input/output fast switch select input BLUE input GREEN input RED input I2C-bus output) Fscomb HPLL C Y/CVBS AGND FILTref CPLL XTAL XTAL2 SECref 23 24 25 26 27 28 29 30 31 32 comb filter status input/output horizontal PLL filter chrominance input luminance/CVBS input analog ground filter reference decoupling colour PLL filter reference crystal input second crystal input SECAM reference decoupling Fig.2 Pin configuration. address input (CVBS
handbook, halfpage
TDA9143
-(R-Y) -(B-Y) Uin Vin SCL SDA VCC DEC DGND
1 2 3 4 5 6 7 8
32 SECref 31 XTAL2 30 XTAL 29 CPLL 28 FILTref 27 AGND 26 Y/CVBS 25 C
TDA9143
9 24 HPLL 23 Fscomb 22 ADDR (CVBS) 21 R 20 G 19 B 18 F 17 CLP/HA
MGE038
SC 10 VA 11 Yout 12 Vout 13 Uout 14 I/O PORT 15 O PORT/LLC 16
F B G R ADDR (CVBS)
18 19 20 21 22
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
FUNCTIONAL DESCRIPTION The TDA9143 is an controlled, alignment-free PAL/NTSC/SECAM colour decoder/sync processor which has been designed for use with baseband chrominance delay lines. For PALplus and EDTV-2 (60 Hz) signals blanking facilities are included. In the standard operating mode the I2C-bus address is 8A. If the address input is connected to the positive supply rail the address will change to 8E. Input switch CAUTION The voltage on the chrominance pin must never exceed 5.5 V. If it does, the IC enters a test mode. The TDA9143 has a two pin input for CVBS or Y/C signals which can be selected via the I2C-bus. The input selector also has a position in which it automatically detects whether a CVBS or Y/C signal is on the input. In this input selector position, standard identification first takes place on an added Y/CVBS and C input signal. After that, both chrominance signal input amplitudes are checked once and the input with the strongest chrominance burst signal is selected. The input switch status is read out by the I2C-bus via output bit YC. The auto input detector indicates YC = 1 for a VBS input signal (no chrominance component). CVBS output In the standard operating mode with I2C-bus address 8A, a CVBS output signal is available on the address pin, which represents either the CVBS input signal or the Y/C input signal, added into a CVBS signal. RGB colour matrix CAUTION The voltage on the Uin pin must never exceed 5.5 V. If it does, the IC enters a test mode. The TDA9143 has a colour matrix to convert RGB input signals into YUV signals. A fast switch, controlled by the signal on pin F and enabled by I2C-bus via EFS (enable fast switch), can select between these YUV signals and the YUV signals of the decoder. Mode FRGB = 1 (forced RGB) overrules EFS and switches the matrixed RGB inputs to the YUV outputs. I2C-bus
TDA9143
The Y signal is internally connected to the switch. The -(R-Y) and -(B-Y) output signals of the decoder first have to be delayed in external baseband chrominance delay lines. The outputs of the delay lines must be connected to the UV input pins. If the RGB signals are not synchronous with the selected decoder input signal, clamping of the RGB input signals is possible by I2C-bus selection of ECL (external RGB clamp mode) and by feeding an external clamping signal to the CLP pin. Also in external RGB clamp mode the VA output will be in a high impedance OFF-state. The YUV outputs can be put in 3-state mode by bus bit LPS (low power standby mode). Standard identification The standards which the TDA9143 can decode depend upon the choice of external crystals. If a 4.4 MHz and a 3.6 MHz crystal are used then SECAM, PAL 4.4/3.6 and NTSC 4.4/3.6 can be decoded. If two 3.6 MHz crystals are used then only PAL 3.6 and NTSC 3.6 can be decoded. Which 3.6 MHz standards can be decoded depends upon the exact frequencies of the 3.6 MHz crystals. In an application where not all standards are required only one crystal is sufficient; in this instance the crystal must be connected to the reference crystal input (pin 30). If a 4.4 MHz crystal is used it must always be connected to the reference crystal input. Both crystals are used to provide a reference for the filters and the horizontal PLL, however, only the reference crystal is used to provide a reference for the SECAM demodulator. To enable the calibrating circuits to be adjusted exactly, two bits from I2C-bus subaddress 00 are used to indicate which crystals are connected to the IC. The standard identification circuit is a digital circuit without external components. The search loop is illustrated in Fig.3. The decoder (via the I2C-bus) can be forced to decode either SECAM or PAL/NTSC (but not PAL or NTSC). Crystal selection can also be forced. Information concerning standard and which crystal is selected and whether the colour killer is ON or OFF is provided by the read out. Using the forced-mode does not affect the search loop, it does however prevent the decoder from reaching or staying in an unwanted state. The identification circuit skips impossible standards (e.g. SECAM when no 4.4 MHz crystal is fitted) and illegal standards (e.g. in forced mode). To reduce the risk of wrong identification, PAL has priority over SECAM. Only line identification is used for SECAM. For a vertical frequency of 60 Hz, SECAM can be blocked to prevent wrong identification by means of bus bit SAF. 6
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
TDA9143
handbook, full pagewidth
SECAM
c c c
PAL
KILLED
SECAM
KILLED
c
NTSC c
NTSC
KILLED
PAL
KILLED
PAL c
c c c c c NTSC
KILLED
PAL
PAL
KILLED
NTSC
Reference crystal
Second crystal
MGE040
Fig.3 Search loop of the identification circuit.
Integrated filters All chrominance bandpass and notch filters, including the luminance delay line, are an integral part of the IC. The filters are gyrator-capacitor type filters. The resonant frequency of the filters is controlled by a circuit that uses the active crystal to tune the SECAM Cloche filter during the vertical flyback time. The remaining filters and the luminance delay line are matched to this filter. The filters can be switched to either 4.43 MHz, 4.29 MHz or 3.58 MHz. The switching is controlled by the standard identification circuit. The luminance notch used for SECAM has a lower Q-factor than the notch used for PAL/NTSC. The notches are provided with a little preshoot to obtain a symmetrical step response. In Y/C mode the chrominance notch filters are bypassed, to preserve full signal bandwidth. For a CVBS signal the chrominance notch filters can be bypassed by bus selection of bit TB (trap bypass). The delay of the colour difference signals -(R-Y) and -(B-Y) in the chrominance signal path and the external chrominance delay lines when used, can be fitted to the luminance signal by I2C-bus in 40 ns steps.
The typical luminance delay can be calculated: delay 90 + SAKSBK {170 + 40(FRQTB)} + 160(YD3) + 160(YD2) + 80(YD1) + 40(YD0) [ns]. Colour decoder The PAL/NTSC demodulator employs an oscillator that can operate with either crystal (3.6 MHz or 4.4 MHz). If the I2C-bus indicates that only one crystal is connected, it will always connect to the crystal on the reference crystal input (pin 30). The Hue signal which is adjustable by I2C-bus, is gated during the burst for NTSC signals. The SECAM demodulator is an auto-calibrating PLL demodulator which has two references. The reference crystal, to force the PLL to the desired free-running frequency and the bandgap reference, to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search mode or in SECAM mode.
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
If the reference crystal is not 4.4 MHz the decoder will not produce the correct SECAM signals. Especially for NTSC applications an internal bypass mode of the external baseband delay line (for instance TDA4665) is added, controlled by bus bit BPS (bypass mode) and with a gain of 2. The bypass mode is not available for SECAM. Comb filter interfacing The frequency of the active crystal is fed to the Fscomb output, which can be connected to an external comb filter IC (e.g. SAA4961). When bus bit ECMB is LOW, the subcarrier frequency is suppressed and its DC value is LOW. With ECMB HIGH, the DC value is HIGH with the subcarrier frequency present, and I2C-bus output bit YC and the input switch are always forced in the Y/C mode, unless an external current sink (e.g. from the comb filter) prevents this, as pin Fscomb also acts as input pin. In this event the subcarrier frequency is still present on the same DC HIGH level. PALplus and EDTV-2 helper blanking For blanking of PALplus or EDTV-2 helper lines, the helper blanking can extend the vertical blanking of the Y, R-Y and B-Y outputs. Additional helper blanking bits (HOB, HBC) and norm/not norm (NRM) indication determine whether the helper signal has to be blanked or conditionally blanked depending on the signal-to-noise ratio bit SNR. Table 1 is valid in a 50 Hz or 60 Hz mode. Table 1 HOB 0 1 1 1 Helper blanking modes HBC X 0 1 1 SNR X X 0 1 HELPER BLANKING OFF ON OFF ON
TDA9143
Provided a NORM sync condition is present, with bus bit HBO = 1 and HBC = 0 blanking is activated. Conditional blanking is possible with HBO = 1 and HBC = 1 and SNR = 1. The black level of the luminance signal is internally clamped with a large time constant to an internal reference black level. This black level is used as fill-in value for the Y signal during blanking. Fast blanking detector To detect the presence of a fast blanking signal, a circuit is added which indicates this event if in more than one line per field a blanking pulse is present at the fast blanking input (F). More than one line per field is chosen to prevent switching-off at every spike detected on the fast blanking input. The detector output FBA (fast blanking active) can be read-out by the I2C-bus. Blanked/unblanked sync By means of the I2C-bus bit BSY (blanked sync) output signal Yout will be presented with or without its composite sync part. At BSY = 0 the composite sync is present on Yout. When activated, helper blanking takes place only during helper lines scan. At BSY = 1 the black level is filled in during the line blanking interval and vertical blanking interval. When activated, the helper blanking extends the vertical blanking. Sync processor (1 loop) The main part of the sync circuit is an oscillator running at 440 x fH (6.875 MHz), provided that I2C-bus address 8A is used or 432 x fH (6.75 MHz) for 8E. Its frequency is divided by 440 or 432 to lock the 1 loop to the incoming signal. The time-constant of the loop can be selected by the I2C-bus (fast, auto or slow). In the fast mode the fast time-constant is chosen independent of signal conditions. In the auto mode the medium time-constant is present with a fast time constant during the vertical retrace period (`field boost'). If the noise detector indicates a noisy video signal the time-constant switches to slow with a smaller field boost, which is also the time-constant for the slow mode. In case of a slow time constant sync gating takes place in a 6 s window around the separated sync pulse. In case of no sync lock, both the auto and the slow mode have a medium time constant, to ensure reliable catching. The noise content of the video signal is determined by a noise detector circuit. This circuit measures the noise at top sync during a 15 line period every field (65 lines after start VA pulse). When the noise level supersedes the
For PALplus (50 Hz, 625 lines) outside the letter box area blanking is possible and takes place on lines 275 to 371 and 587 to 59. For EDTV-2 (system M, 60 Hz, 525 lines) outside the letter box area blanking is possible and takes place on lines 230 to 312 and 493 to 49 (1).
(1) For system M, line numbers start with the first equalizing pulse in field 1, but the internal line counter starts counting at the first vertical sync pulse in field 1. This line number notation is used here and in Fig.7.
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
detector threshold in two consecutive fields, noise is indicated and bus bit SNR is set. The free-running frequency of the oscillator is determined by a digital control circuit that is locked to the active crystal. When a power-on-reset pulse is detected the frequency of the oscillator is switched to a frequency of about 10 MHz (23 kHz horizontal frequency) to protect the horizontal output transistor. The oscillator frequency is calibrated to 6.875 MHz or 6.75 MHz after receiving data on subaddress 01 for the first time after power-on-reset detection. To ensure that this procedure does not fail it is absolutely necessary to send subaddress 00 before subaddress 01. Subaddress 00 contains the crystal indication bits and when subaddress 01 is received the line oscillator calibration will be initiated (for the start-up procedure after power-on-reset detection, see the I2C-bus protocol). The calibration is terminated when the oscillator frequency reaches 6.875 MHz or 6.75 MHz. The 1 loop can be opened using the I2C-bus. This is to facilitate On Screen Display (OSD) information. If there is no input signal or a very noisy input signal, the 1 loop can be opened to provide a stable line frequency, and thus a stable picture.
TDA9143
The sync part also delivers a two-level sandcastle signal, which provides a combined horizontal and vertical blanking signal and a clamping pulse for the display section of the TV. MACROVISION sync gating A dedicated gating signal for the separated sync pulses, starting 11 lines after the detection of a vertical sync pulse until picture scan starts, can be used to improve the behaviour of the horizontal PLL with respect to the unwanted disturbances caused by the pseudo-sync pulses in video signals with MACROVISION anti-copy guard signals. This sync gating excludes the pseudo-sync pulses and can only take place in the auto and fast 1 time constant mode, provided I2C-bus bit SNR = 0 and I2C-bus bit EMG = 1. I2C-bus bit EMG = 1 enables and EMG = 0 disables this sync gating in the horizontal PLL. Vertical divider system The vertical divider system has a fully integrated vertical sync separator. The divider can accommodate both 50 Hz and 60 Hz systems; it can either determine the field frequency automatically or it can be forced to the desired system via the I2C-bus. A block diagram of the vertical divider system is illustrated in Fig.4.
handbook, halfpage
LINE COUNTER
CONTROLLER
TIMING GENERATOR
NORM COUNTER
MGE043
Fig.4 Block diagram of the vertical divider system.
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
The divider system operates at twice the horizontal frequency. The line counter receives enable pulses at this frequency, thereby counting two pulses per line. A state diagram of the controller is shown in Fig.5. Because it is symmetrical only the right-hand part will be described. Depending on the previously found vertical frequency, the controller will be in one of the COUNT states. When the line counter has counted 488 pulses (i.e. 244 lines of the video input signal), the controller will move to the next state depending on the output of the norm counter. This can be either NORM, NEAR_NORM or NO_NORM, depending
TDA9143
on the position of the vertical sync pulse in the previous fields. When the controller is in the NORM state it generates the vertical sync pulse (VSP) automatically and then, when the line counter is at LC = 626, moves to the WAIT state. In this condition it waits for the next pulse of the double line frequency signal, and then moves to the COUNT state of the current field frequency. When the controller returns to the COUNT state, the line counter will be reset half a line after the start of the vertical sync pulse of the video input signal. The NORM window normally looks within one line width and a sudden half line delay of the vertical sync pulse change can therefore be neglected.
handbook, full pagewidth
else
NO NORM no_norm no_norm
LC = 528 or LC = 576 or on VSP LC = 628 or LC = 722 or on VSP
LC < 488 COUNT on SYNC if LC < 576 WAIT FOR RESET PULSE on SYNC if LC 576 COUNT
LC < 488
LC = 526 norm
LC = 626 norm
NORM near_norm LC 525
NORM near_norm LC 625
on VSP if 522 < LC < 528 or on LC = 528
NEAR NORM
NEAR NORM
on VSP if 622 < LC < 628 or on LC = 628
LC < 522
LC < 622
vertical frequency 60 Hz
vertical frequency 50 Hz
MGE042
Fig.5 State diagram of the vertical divider system.
1996 Jan 17
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
When the controller is in the NEAR_NORM state it will move to the COUNT state if it detects the vertical sync pulse within the NEAR_NORM window (i.e. 622 < LC < 628). If no vertical sync pulse is detected the controller will move back to the COUNT state when the line counter reaches LC = 628. The line counter will then be reset. When the controller is in the NO_NORM state, it will move to the COUNT state when it detects a vertical sync pulse and reset the line counter. If a vertical sync pulse is not detected before LC = 722 (if the 1 loop is locked in forced mode) it will move to the COUNT state and reset the line counter. If the 1 loop is not locked the controller will return to the COUNT state when LC = 628. The forced mode option keeps the controller in either the left-hand side (60 Hz) or the right-hand side (50 Hz) of the state diagram. Figure 6 illustrates the state diagram of the norm counter which is an up/down counter that increases its counter value by 1 if it finds a vertical sync pulse within the selected
TDA9143
window. If not, it decreases the counter value by 1 (or 2, see Fig.6). In the NEAR_NORM and NORM states the first correct vertical sync pulse after one or more incorrect vertical sync pulses is processed as an incorrect pulse. This procedure prevents the system from staying in the NEAR_NORM or NORM state if the vertical sync pulse is correct in the first field and incorrect in the second field. In case of no sync lock (SLN = 1) the norm counter is reset to NO_NORM (wide search window), for fast vertical catching when switching between video sources. Fast switching between different channels however can still result in a continuous horizontal sync lock situation, when the channel is changed before the norm counter has reached the NORM state. To provide faster vertical catching in this case, measures have been taken to prevent the norm counter to count down to zero before reaching the NO_NORM state (see left-hand of Fig.6). Bus bit FWW (forced wide window) enables the norm counter to stay in the NO_NORM state if desired. The norm/no_norm status is read out by bus bit NRM.
handbook, full pagewidth
22 < NC 27
0 NC < 12
NORM
NC = 22 (RESET NC)
NO NORM
NC = 26
10 < NC < 26(1)
NC = 17
NEAR NORM 10 < NC < 17
(R
NC ES = 1 ET 0 NC )
NEAR NORM
0 = 1 C) NC T N E ES (R
NC = 0
NC = 12
NC = 14
NEAR NORM 0 < NC < 14
norm test area
near_norm test area
MGE041
(1) VSP found: count 1 up; no VSP found: count 2 down.
Fig.6 State diagram of the norm counter.
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
Output port and in/output port Two stand-alone ports are available for external use. These ports are I2C-bus controlled, the output port by bus bit OPB and the input/output port by bus bit OPA. Bus bit OPA is an open-drain output, to enable input port functionality. The pin status is read out by bus via output bit IP. Sandcastle
TDA9143
Figure 7 illustrates the timing of the acquisition sandcastle (ASC) and the VA pulse with respect to the input signal. The sandcastle signal is according to the two-level 5 V sandcastle format. An external vertical guard current can overrule the sink current to enable blanking purposes.
2nd handbook, full pagewidth FIELD 625
1st FIELD
50 Hz
23
ASC VA 1st FIELD 312
(1)
2nd FIELD
336
ASC
2nd FIELD 525
1st FIELD
60 Hz
17
ASC VA
1st FIELD 262
2nd FIELD
280
ASC
MBG902
(1) See Vertical Section in "Characteristics"
Fig.7 Acquisition sandcastle signal and VA pulse timing diagram.
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
I2C-bus
TDA9143
For address 8A, an unconnected pin 22 is sufficient as this pin is also a CVBS output. Do not short-circuit the input to ground. If the address input is connected to the positive supply rail, the address changes from 8A to 8E. Table 2 Slave address (8A) A6 1 A5 0 A4 0 A3 0 A2 1 A1 X A0 1 R/W X
SLAVE ADDRESS 8A
Valid subaddresses: 00 to 03 and 17 to 18 (Hex). Only the five least significant bits of the subaddress bytes are recognized. Auto-increment mode is available for subaddresses. The output addresses 00 and 01 can only be read in auto-increment mode. The I2C-bus transceiver is designed for a maximum clock frequency (fSCL) of 100 kHz. Table 3 Input bytes MSB D7 INA FORF EFS LCA . - BPS D6 INB FORS ECL FWW . - LPS D5 TB OPA HU5 - . HOB FRGB DATA BYTE D4 ECMB OPB HU4 - . HBC EMG D3 FOA POC HU3 - . BSY YD3 D2 FOB FM HU2 - . - YD2 D1 XA SAF HU1 - . - YD1 LSB D0 XB FRQF HU0 - . - YD0
SUB ADDRESS 00 01 02 03 . 17 18 Table 4
Output (status) bytes D7 POR - D6 FSI - D5 YC - D4 SL FBA D3 IP NRM D2 SAK SNR D1 SBK SXA D0 FRQ SXB
OUTPUT ADDRESS 00 01
Start up procedure: read the status byte until POR = 0; send subaddress 18 with the LPS bit indicating normal operation (LPS = 0); send subaddress 00 with the crystal indicator bits (XA and XB) indicating that only one crystal is connected to the IC(1); wait for 50 ms; send subaddress 01; wait for at least 50 ms; set XA,XB to the actual crystal configuration. Each time before the data in the IC is refreshed, the status byte must be read. If POR = 1, then the above procedure must be carried out to restart the IC. As long as POR = 1, sending subaddress 01 does not start the line oscillator calibration. POR is reset when the status register is read out and can only be reset when the supply voltages exceed the POR detection levels mentioned in the Bias Generator characteristics (see Chapter "Characteristics"). Failure to stick to the above procedure may result in an incorrect horizontal frequency after power-up or a power-dip. Remark: if the presence of output signals HA/CLP and/or VA is required after power-up of the IC, subaddress 02 with the ECL bit indicating ECL = 0 must be sent before sending subaddress 00.
(1) To be absolutely sure that the line oscillator is calibrated with the appropriate crystal frequency data, it is possible to check the received values of the crystal indication bits via status bits SXA and SXB.
1996 Jan 17
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Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
INPUT SIGNALS Table 5 INA 0 0 1 Note 1. When ECMB = 1 and no current is drawn from the Fscomb pin, source select is forced to be YC. Table 6 TB 0 1 Note 1. The chrominance trap is always bypassed in YC mode. Table 7 ECMB 0 1 Table 8 FOA 0 0 1 Table 9 XA 0 0 1 1 Comb filter enable CONDITION comb filter disabled comb filter enabled 1 time constant FOB 0 1 - auto slow fast MODE trap bypassed Trap bypass; note 1 CONDITION trap not bypassed Table 12 Output value O port OPB 0 1 LOW HIGH LEVEL Source select; note 1 INB 0 1 - CVBS YC auto CVBS/YC SOURCE Table 10 Forced field frequency FORF 0 0 1 1 FORS 0 1 0 1 60 Hz 50 Hz
TDA9143
FIELD FREQUENCY auto; 60 Hz if no lock
auto; 50 Hz if no lock
Table 11 Output value I/O port OPA 0 1 LOW HIGH LEVEL
Table 13 1 loop control POC 0 1 1 loop closed 1 loop open CONDITION
Table 14 Forced standard; note 1 FM 0 1 1 1 1 CRYSTAL Note 1. If XA and XB indicate that only one crystal is connected to the IC and FM and FRQF force it to use the second crystal, then colour will be switched off. When SAF = 0, SECAM 60 Hz is disabled; when SAF = 1, SECAM 60 Hz is enabled. SAF - 0 0 1 1 FRQF - 0 1 0 1 STANDARD auto search PAL/NTSC second crystal PAL/NTSC reference crystal black and white SECAM reference crystal
Crystal indication XB 0 1 0 1 2 x 3.6 MHz 1 x 3.6 MHz 1 x 4.4 MHz 1 x 3.6 MHz and 1 x 4.4 MHz
1996 Jan 17
14
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
Table 15 Enable fast switch EFS 0 1 CONDITION fast switch disabled fast switch enabled, when FRGB = 0
TDA9143
Table 22 PALplus/EDTV-2 helper blanking (Y, U, V) HOB 0 1 1 1 HBC - 0 1 1 SNR - - 0 1 BLANKING off on off on
Table 16 External RGB clamp mode ECL 0 1 CONDITION off; internal clamp pulse is used on; external clamp pulse has to be supplied to CLP pin
Table 23 Blanked sync on Yout BSY 0 1 unblanked sync blanked sync CONDITION
Table 17 Forced RGB mode FRGB 0 1 forced RGB CONDITION YUV, when disabled via EFS
Table 24 Baseband delay line bypass; note 1. BPS 0 1 Note 1. SECAM cannot be bypassed. Table 25 Low power standby mode LPS 0 1 CONDITION normal operation low power standby no bypass baseband delay line bypassed CONDITION
Table 18 YUV outputs as a function of EFS, FRGB and Fast switch F EFS 0 - 1 1 Table 19 Hue FUNCTION Hue ADDRESS HU5 to HU0 DIGITAL NUMBER 000000 = -45 111111 = +45 Table 20 Line-locked clock active LCA 0 1 LLC/HA mode CONDITION OPB/CLP mode FRGB 0 1 0 0 F - - 0 1 SELECTED INPUTS YUV RGB YUV RGB
Table 26 Enable MACROVISION gating EMG 0 1 disable gating enable gating CONDITION
Table 27 Luminance delay control YD3 to YD0 0000 1111 -280 ns +160 ns CONDITION
Table 21 Forced wide window FWW 0 1 CONDITION auto window mode forced wide window
1996 Jan 17
15
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
OUTPUT SIGNALS Table 28 Power-on reset POR 0 1 normal mode power-down mode CONDITION Table 34 Fast blanking active FBA 0 1
TDA9143
CONDITION no fast blanking detected fast blanking detected
Table 29 Field frequency indication FSI 0 1 50 Hz 60 Hz CONDITION
Table 35 Norm/no_norm indication in vertical divider system NRM 0 1 norm CONDITION no_norm or near_norm
Table 30 Input switch mode YC 0 1 CVBS mode Y/C mode CONDITION Table 36 Signal-to-noise ratio SNR 0 1 Table 31 1 lock indication SL 0 1 not locked locked CONDITION Table 37 Crystal indication read-out SXA 0 0 Table 32 Input value I/O port IP 0 1 LOW HIGH LEVEL 1 1 SXB 0 1 0 1 CRYSTAL 2 x 3.6 MHz 1 x 3.6 MHz 1 x 4.4 MHz 1 x 3.6 MHz and 1 x 4.4 MHz S/N > 20 dB S/N < 20 dB CONDITION
Table 33 Standard read-out SAK 0 0 0 0 1 1 1 SBK 0 0 1 1 0 0 1 FRQ 0 1 0 1 0 1 - STANDARD PAL second crystal PAL reference crystal NTSC second crystal NTSC reference crystal illegal forced mode SECAM reference crystal colour off
1996 Jan 17
16
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCC ICC Ptot Tstg Tamb PARAMETER supply voltage supply current total power dissipation storage temperature operating ambient temperature CONDITIONS - - - -55 -10 MIN. - - - - - TYP.
TDA9143
MAX. 9.0 70 630 +150 +70
UNIT V mA mW C C
THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air 48 VALUE K/W UNIT
QUALITY SPECIFICATION Quality level in accordance with "SNW-FQ-611-E" is applicable for ESD protection, human body model: 3000 V, 100 pF, 1500 on all pins. Machine model: 300 V, 200 pF, 0 on all pins. The number of the quality specification can be found in the "Quality Reference Handbook". The handbook can be ordered using the code 9397 750 00192.
1996 Jan 17
17
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
CHARACTERISTICS VCC = 8 V; Tamb = 25 C; I2C-bus address 8A; unless otherwise specified. SYMBOL Supply (pin 7) VCC ICC Ptot ICC Input switch Caution: the voltage on pin 25 must never exceed 5.5 V, if it does, the IC enters a test mode Y/CVBS INPUT (PIN 26) Vi(p-p) Zi Ci Ii(bias) Vi(p-p) Zi Ci Vo(p-p) Zo B Vtsl VD(DEC) Vdet(CC) Vdet(DEC) IL(DEC) input voltage (peak-to-peak value) input impedance input capacitance input bias current top sync-white - 60 - - - 60 - top sync-white CL = 15 pF - - 7 2.2 1.0 - - 3.3 supply voltage supply current total power dissipation low power supply current 7.2 50 360 12 8.0 60 480 16 PARAMETER CONDITIONS MIN. TYP.
TDA9143
MAX.
UNIT
8.8 70 620 22
V mA mW mA
1.43 - 5 - 0.6 - 5 - 500 - 3.4
V k pF A V k pF
C INPUT (PIN 25) input burst voltage (peak-to-peak value) input impedance input capacitance 0.3 - - 1.0 - - 2.8
CVBS OUTPUT (PIN 22); ONLY FOR ADDRESS 8A output voltage (peak-to-peak value) output impedance bandwidth at -3 dB top-sync voltage level V MHz V
Bias generator (pin 8) digital supply voltage POR detection level for power supply POR detection level for DEC pin current load on digital supply sum of pins 8, 11, 16, 17 4.8 5.7 4.0 - 5.0 6.0 4.3 - 5.2 6.3 4.6 2.0 V V V mA
Subcarrier regeneration GENERAL; note 1 CR catching and holding range reference crystal second crystal Zi phase shift for 80% deviation of catching range input impedance reference crystal and second crystal 0.80 1.00 1.20 k 500 450 - - - - - - 5 Hz Hz deg
1996 Jan 17
18
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
SYMBOL FSCOMB OUTPUT (PIN 23) Vsub(p-p) Vcen Vcdis Isink RGND ACC ACC control range change of -(R-Y) and -(B-Y) signals over range colour killer treshold PAL/NTSC SECAM kill/unkill hysteresis Demodulators -(R-Y) and -(B-Y) outputs (pins 1 and 2) GENERAL ratio of -(B-Y) to -(R-Y) TC temperature coefficient of -(R-Y) and -(B-Y) amplitude spread of -(R-Y) to -(B-Y) ratio between standards V-(R-Y) V-(B-Y) B Zo VCC V-(R-Y)(p-p) V-(B-Y)(p-p) Vres(p-p) Vres(p-p) Vres(p-p) S/N output level of -(R-Y) output during blanking level output level of -(B-Y) output during blanking level bandwidth at -3 dB output impedance supply voltage dependence hue phase shift (NTSC only) -(R-Y) output voltage (peak-to-peak value) -(B-Y) output voltage (peak-to-peak value) standard colour bar 1.20 - -1 1.7 1.7 600 - - 35 standard colour bar standard colour bar 480 610 - - - 46 1.27 - - 2.1 2.0 670 - - 45 540 685 - - - - -34 -31 - -31 -28 3 -20 - - - subcarrier output voltage amplitude (peak-to-peak value) comb enable voltage level comb disable voltage level sink current to undo forced Y/C mode of input switch value of grounded resistor to undo forced Y/C mode of input switch CL = 15 pF 150 4.0 - 0.4 4 200 4.2 0.1 - - PARAMETER CONDITIONS MIN. TYP.
TDA9143
MAX.
UNIT
300 5.0 1.4 1.0 10
mV V V mA k
+6 1
dB dB
-28 -25 -
dB dB dB
1.34 0.1 +1 2.5 2.5 750 500 2 55 605 765 15 20 tbf - %/K dB V V kHz %/V deg
PAL/NTSC DEMODULATOR mV mV mV mV mV dB
8.8 MHz residue (peak-to-peak value) both outputs 7.2 MHz residue (peak-to-peak value) both outputs 4.4 and 3.6 MHz residue signal-to-noise ratio both outputs 0 to 1 MHz
1996 Jan 17
19
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
SYMBOL PAL DEMODULATOR VR(p-p) V-(R-Y)(p-p) V-(B-Y)(p-p) fos S/N Vres(p-p) fpole Vcal NL Filters TUNING Vtune td(on) tuning voltage 1.5 3
1 2H
TDA9143
PARAMETER
CONDITIONS
MIN. - -
TYP. - - 1.08 1.37 - - - 85 3 4 -
MAX.
UNIT
ripple (peak-to-peak value)
20 5
mV deg
demodulator phase error -(R-Y) output voltage (peak-to-peak value) -(B-Y) output voltage (peak-to-peak value) black level offset frequency signal-to-noise ratio 7.8 MHz to 9.4 MHz residue (peak-to-peak value) pole frequency of de-emphasis ratio of pole and zero frequency calibration voltage non linearity 0 to 1 MHz
SECAM DEMODULATOR standard colour bar standard colour bar 0.96 1.22 - 40 - 77 - 3 - 1.21 1.53 7 - 30 93 - 5 3 V % V V kHz dB mV kHz
6
V
LUMINANCE DELAY; YD3 to YD0 = 1011 delay time colour on fsc = 3.6 MHz; TB = 0 fsc = 3.6 MHz and 4.4 MHz; TB = 1 td(off) td(tun) fo delay time colour off delay time tuning range 15 steps YD3 to YD0; note 2 555 515 350 -280 3.53 4.37 4.23 2.60 3.20 2.90 26 580 540 370 - 3.58 4.43 4.29 not active 2.80 3.50 3.20 - 3.58 4.43 1.20 1.40 3.00 3.80 3.50 - 3.76 4.65 1.35 1.55 MHz MHz MHz dB 605 565 390 +160 ns ns ns ns
CHROMINANCE TRAP notch frequency fsc = 3.6 MHz fsc = 4.4 MHz SECAM Y/C and B/W mode B bandwidth at -3 dB fsc = 3.6 MHz fsc = 4.4 MHz SECAM fsc(sup) fres B subcarrier suppression CHROMINANCE BANDPASS resonant frequency bandwidth at -3 dB fsc = 3.6 MHz fsc = 4.4 MHz fsc = 3.6 MHz fsc = 4.4 MHz 3.40 4.21 1.05 1.25 MHz MHz MHz MHz 3.63 4.49 4.35 MHz MHz MHz
1996 Jan 17
20
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
SYMBOL CLOCHE FILTER fres B resonant frequency bandwidth at -3 dB SECAM SECAM 4.26 241 4.29 268 PARAMETER CONDITIONS MIN. TYP.
TDA9143
MAX.
UNIT
4.31 295
MHz kHz
Sync input (pin 26) VIDEO INPUT VY/CVBS(p-p) sync pulse amplitude (peak-to-peak value) slicing level td Nth H td delay of sync pulse due to internal filter noise detector threshold level hysteresis delay between internally separated vertical sync pulse and video signal 35 40 0.2 18 2 12 300 47 0.3 20 3 18.5 600 55 0.4 22 5 27 mV % s dB dB s
Horizontal section CLP OUTPUT (OPB/CLP MODE); HA OUTPUT (LLC/HA) MODE (BOTH ON PIN 17) VOH VOL Isink Isource tW(HA) td tW(CLP) td f VCC fCR fHR fo HIGH level output voltage LOW level output voltage sink current source current HA pulse width (32 LLC pulses) delay between middle of horizontal sync pulse and middle of HA CLP pulse width (25 LLC pulses) delay between middle of horizontal sync pulse and start of CLP pulse 6 jitter note 3 1 in auto mode note 3 4.0 - 2 2 - 0.3 - 3.0 - - - 625 - - 5 0.2 - - 4.65 0.45 3.65 3.2 - - 40 - - - 5.5 0.4 - - - 0.6 - 3.4 5 V V mA mA s s s s ns
FIRST LOOP (1) frequency deviation when not locked supply voltage dependence catching range holding range static phase shift 1.5 - - 1.0 0.1 % Hz/V Hz kHz s/kHz
LLC OUTPUT (PIN 16); LLC/HA MODE output frequency 440 x fH 440 x fH Vo(p-p) output amplitude (peak-to-peak value) 50 Hz standard 60 Hz standard - - 0.25 6.875 6.923 - - - - MHz MHz V
1996 Jan 17
21
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
SYMBOL Vo td PARAMETER DC output voltage level delay between negative edge of LLC and positive edge of HA pulse CL = 15 pF CONDITIONS MIN. - 10 TYP. 2.5 20
TDA9143
MAX. - 40
UNIT V ns
Vertical section VERTICAL OSCILLATOR ffr fLR LR free running frequency frequency locking range divider locking range FORF = 1; divider ratio 628 FORF = 0; divider ratio 528 - - 43 488 50 60 - 625 - - 64 722 Hz Hz Hz
VA OUTPUT (PIN 11); ECL = 0 VOH VOL Isink Isource tW(VA) HIGH level output voltage LOW level output voltage sink current source current VA pulse width 2.5/fH 3/fH td Zo Vo Isink Vbl Isource Iext tW(H) td delay between start of vertical sync pulse and positive edge of VA output impedance 50 Hz standard 60 Hz standard note 4; see Fig.7 ECL = 1 - - - 3 160 192 35 - - - - - s s s M 4.0 - 2 2 5 0.2 - - 5.5 0.4 - - V V mA mA
Sandcastle output (pin 10) zero level output voltage sink current 0 0.5 0.5 0.7 1 0.9 V mA
HORIZONTAL AND VERTICAL BLANKING blanking voltage level source current external current required to force the output to the blanking level horizontal blanking pulse width delay between start of horizontal blanking and start of clamping pulse 69 LLC pulses 44 LLC pulses 2.2 0.5 1.0 - - 2.5 0.7 - 10.0 6.4 2.8 0.9 3.0 - - V mA mA s s
CLAMPING PULSE Vclamp Isource tW(clamp) td clamping voltage level source current clamping pulse width delay between middle sync of input and start of clamping pulse 25 LLC pulses note 3 4.2 0.5 - 3.0 4.5 0.7 3.6 3.2 4.8 0.9 - 3.4 V mA s s
1996 Jan 17
22
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9143
MAX.
UNIT
YUV/RGB switches; note 5 Caution: the voltage on pin 3 must never exceed 5.5 V, if it does, the IC enters a test mode RGB INPUTS (PINS 21, 20, AND 19 RESPECTIVELY); note 5 Vi(p-p) Zi Ci Vi(p-p) Vi(p-p) Zi Ci Vo(p-p) Vo(p-p) Zo Vo S/N Vos Gv input voltage (peak-to-peak value) input impedance input capacitance - 3 - - - 3 - black-white black-white black level f = 0 to 5 MHz - - - 2.7 - - 0.7 - - 1.33 1.05 - - 1.00 0.80 - 3.0 52 - 1 - 5 V M pF
UV INPUTS (PINS 3 AND 4 RESPECTIVELY); note 5 U input voltage (peak-to-peak value) V input voltage (peak-to-peak value) input impedance (both inputs) input capacitance (both inputs) 1.90 1.50 - 5 - - 250 3.3 - 10 V V M pF
Y OUTPUT (PIN 12) U output voltage PALplus output voltage output impedance DC output voltage level signal-to-noise ratio offset voltage Yblack to re-inserted black voltage gain from Y/CVBSi to Yo UV OUTPUTS (PINS 14 AND 13); note 5 Vo(p-p) Vo(p-p) Zo Vo Gv U output voltage (peak-to-peak value) V output voltage (peak-to-peak value) output impedance (both outputs) DC output voltage level voltage gain from Uin to Uout from Vin to Vout GENERAL Vdiff difference between black levels of YUV outputs in RGB mode and YUV mode non-linearity bandwidth at -3 dB crosstalk between RGB and UVin signals on UVout sync locked mixed RGB/YUV - via fast blanking any input to any output any input to any output; CL = 15 pF f = 0 to 5 MHz - 7 - - 10 mV 0.94 0.94 0.97 0.97 1.00 1.00 - - - 2.3 1.33 1.05 - 2.6 1.90 1.50 250 2.9 V V V 1.35 1.43 1.50 V V V dB mV
NL B c
- - -
5 - -50
% MHz dB
1996 Jan 17
23
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
SYMBOL B tclamp VIL VIH td VIL VIH tW(clamp) Vos(clamp) Zi Gv PARAMETER bandwidth at -1 dB internal Y clamping time constant CONDITIONS any input to any output; CL = 15 pF MIN. 5 - UV switched on RGB switched on between F and YUV 0 0.9 - 0 2.4 1.8 - ECL = 1 3 TYP. - 10 - - - - - 3.5 - -
TDA9143
MAX. - - 0.5 3.0 20
UNIT MHz ms
FAST SWITCH F (PIN 18) LOW level input voltage HIGH level input voltage switching delay V V ns
EXTERNAL CLAMP INPUT (PIN 17) LOW level input voltage (pin CLP) HIGH level input voltage (pin CLP) clamping pulse width clamping offset voltage on UV outputs input impedance no clamping clamping note 6 0.6 5.5 - 10 - V V s mV M
Colour matrix voltage gain from R to Yout from G to Yout from B to Yout from R to Uout from G to Uout from B to Uout from R to Vout from G to Vout from B to Vout Output and in/output port O PORT (PIN 16); OPB/CLP MODE VOH VOL Isink Isource VOH VOL Isink VIH VIL HIGH level output voltage LOW level output voltage sink current source current 4.0 - 100 100 - - 2 2.0 - 5 0.2 - - - 0.2 - - - 5.5 0.4 - - VCC 0.4 - - 0.6 V V A A V V mA V V 0.41 0.80 0.15 0.41 0.80 1.21 0.95 0.80 0.15 0.43 0.84 0.16 0.43 0.84 1.27 1.00 0.84 0.16 0.45 0.88 0.17 0.45 0.88 1.33 1.05 0.88 0.17
I/O PORT; OPB/CLP MODE HIGH level output voltage LOW level output voltage sink current HIGH level input voltage LOW level input voltage
1996 Jan 17
24
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
Notes to the characteristics
TDA9143
1. All frequency variations are referred to 3.58 MHz or 4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9920 520 0047x and 9920 520 0048x. The oscillator circuit is insensitive to the spurious responses of the crystal. The typical crystal parameters for the crystals mentioned above are: a) Load resonance frequency f0 = 4.433619 MHz or 3.579545 MHz (CL = 20 pF). b) Motional capacitance CM = 20.6 x fF (4.43 MHz crystal) or 14.7 x fF (3.58 MHz crystal). c) Parallel capacitance C0 = 5 pF for both crystals. d) The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and the general specifications given for the subcarrier regeneration are therefore valid for the specified crystal series. In the figure tolerances of the crystal with respect to nominal frequency, motional capacitance and ageing have been taken into account and have been counted for by Gaussian addition. Whenever different typical crystal parameters are used, the following equation might be helpful for calculating the impact on the detuning capabilities: CM e) Detuning range proportional to: ------------------------- CO 2 1 + ------- CL f) The resulting detuning range should be corrected for temperature shift and supply deviation of both the IC and the crystal. For the above mentioned crystals, the actual load capacitance in the application should be CL = 18 pF to account for parasitic capacitance on and off chip. For 3-norm applications with two crystals connected to one pin, the maximum load capacitance of the crystal pin should not exceed 12 pF. 2. YD3 and YD2 are equal significant bits, both representing a 160 ns delay step. YD1 represents 80 ns and YD0 represents a 40 ns delay step. 3. This delay is partially caused by the low-pass filter at the sync separator input. 4. The delay between the positive edge of VA and the first negative edge of HA (or positive edge of CLP) after VA is 1 34.5 s for field 1 and 2.5 s for field 2 (17 LLC pulses with or without ------------- respectively). 2 x fH 5. The output signals of the demodulator are called -(R-Y) and -(B-Y) in this specification. The colour difference input and output signals of the YUV switch are called UV signals. However, these signals do not have the amplitude correction factor of real UV signals. They are called UV signals and not -(R-Y) and -(B-Y) to prevent confusion between the colour difference signals of the demodulator and the colour difference signals of the YUV switch. 6. The maximum external clamping pulse width is the minimum available blanking level time of the supplied RGB signals.
1996 Jan 17
25
1996 Jan 17
Y/CVBS 82 k 100 nF GND 18 pF 18 pF 3.3 nF 15 k 470 nF 3.3 nF C 75 75 100 nF 100 nF 100 nF 27 26 25 100 nF 24 32 31 30 29 28
TEST AND APPLICATION INFORMATION
Philips Semiconductors
handbook, full pagewidth
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
ADDR (CVBS) R G B F CLP/HA
Fscomb
75
75
75
75
100 nF 23 22 21 20
100 nF 19
100 nF 18 17
TDA9143
1 100 nF 100 F 8V 5V 2 100 nF 3 100 nF 4 100 nF 5 100 6 100 7 8 100 nF 9 10 11 12 13 14 15 16
26
240 5V1 100 nF 1
14 13 12 11 10 9 16 15 14 13 12 11 10 9 TDA4665 2 3 4 5 6 7 8 1 2 PC74HCU04 3 4 5 6
8 100 nF 7
1nF
120 k
LLC interface to TDA9151
SCL
SDA
SC
VA
Yout
Vout
Uout
O PORT/LLC I/O PORT
LCC
HA
MGE044
Preliminary specification
TDA9143
Pins 28 and 32 are sensitive to leakage currents. Keep the analog and digital ground currents well separated. The decoupling capacitor between pins 8 and 9 must be placed as close to the IC as possible.
Fig.8 Application circuit.
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
EQUIVALENT PIN CIRCUITS PIN 1 SYMBOL -(R-Y) EQUIVALENT PIN CIRCUIT
TDA9143
100 0.2 mA
1
MGE046
2
-(B-Y)
100 0.2 mA
2
MGE047
3
Uin
0.07 mA
100 3
MGE048
1996 Jan 17
27
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
PIN 4 Vin
CLIN DCT 100 4 0.07 mA
TDA9143
SYMBOL
EQUIVALENT PIN CIRCUIT
MGE049
5
SCL
5
MGE050
6
SDA
6
MGE051
DATA
7
VCC
7
MGE052
8
DEC
5V
8
MGE053
1996 Jan 17
28
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
PIN 9 SYMBOL DGND EQUIVALENT PIN CIRCUIT
9
TDA9143
MGE054
10
SC
10
MGE055
11
VA
11
MGE056
12
Yout
100 0.5 mA
12
MGE057
1996 Jan 17
29
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
PIN 13 SYMBOL Vout EQUIVALENT PIN CIRCUIT
TDA9143
100 0.5 mA
13
MGE058
14
Uout
100 0.5 mA
14
MGE059
15
I/O PORT
15
MGE060
16
O PORT/LLC
100 16
MGE061
1996 Jan 17
30
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
PIN 17 SYMBOL CLP/HA EQUIVALENT PIN CIRCUIT
TDA9143
17
MGE062
18
F
100 18
MGE064
19 20 21
B G R
0 to 60 A
0 to 60 A
0 to 60 A
CLP 100 100 100
19
20
21
MGE063
1996 Jan 17
31
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
PIN 22 SYMBOL ADDR (CVBS) EQUIVALENT PIN CIRCUIT
TDA9143
100 0.5 mA
22
MGE065
23
Fscomb
100
23
MGE066
24
HPLL
4V
24
4V
MGE067
25
C
25
100 1 M
MGE068
1996 Jan 17
32
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
PIN 26 SYMBOL Y/CVBS EQUIVALENT PIN CIRCUIT
TDA9143
1 k 26 100
3.5 A
MGE069
27 28
AGND FILTref
analog ground
4V INIT 28
MGE071
29
CPLL
29
MGE072
1996 Jan 17
33
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
PIN 30 SYMBOL XTAL EQUIVALENT PIN CIRCUIT
TDA9143
1 k 0.2 mA
30
MGE073
31
XTAL2
1 k 0.2 mA
31
MGE074
32
SECref
32
CAL
MGE075
1996 Jan 17
34
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
PACKAGE OUTLINE SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
TDA9143
SOT232-1
D seating plane
ME
A2 A
L
A1 c Z e b 32 17 b1 wM (e 1) MH
pin 1 index E
1
16
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 29.4 28.5 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT232-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1996 Jan 17
35
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA9143
with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Jan 17
36
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
NOTES
TDA9143
1996 Jan 17
37
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
NOTES
TDA9143
1996 Jan 17
38
Philips Semiconductors
Preliminary specification
I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor
NOTES
TDA9143
1996 Jan 17
39
Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. (31)40-2788399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil, P.O. Box 7383 (01064-970), Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. (852)2319 7888, Fax. (852)2319 7700 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (45)32 88 26 36, Fax. (45)31 57 19 49 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (358)0-615 800, Fax. (358)0-61580 920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 51 40, 20035 HAMBURG, Tel. (040)23 53 60, Fax. (040)23 53 63 00 Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)7640 000, Fax. (01)7640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5130, Fax. (03)3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. (040)2783749, Fax. (040)2788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (63) 2 816 6380, Fax. (63) 2 817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430, Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494 Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (886) 2 382 4443, Fax. (886) 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (66) 2 745-4090, Fax. (66) 2 398-0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 27 70, Fax. (0212)282 67 07 Ukraine: Philips UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. 380-44-4760297, Fax. 380-44-4766991 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181)730-5000, Fax. (0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 (c) Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1100/01/pp40 Document order number: Date of release: 1996 Jan 17 9397 750 00576

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